Cabletron Systems T2015 Specifikace Strana 28

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4-11
Samsung Electronics
Summary of product
Service Manual
USB 2.0
SDRAM
64MB
EEPROM
4k bit
Flash Memory
2MB
NPC / (W-LAN)
Optional
Full Function
Engine
Control
Block
LPEC1
SDRAM DIMM
34MB~128MB
SPGPm
Panel
16x2 LCD
5pinUART
1) CPU BLOCK
This is the heart of the machine. A 120MHz - 32bit RISC processor is used to manage commands
and data supplied by the host. This is converted into a bitmap image which is passed to the engine
block for printing. The CPU is also used to control various other devices e.g. the USB 2.0 Interface
chip.
2) SPGPm overview
* Package
- 272 pins PBGA
* Power
- 1.8V(Core), 3.3V(IO) power operation
- P1284 inputs : 5V tolerant
* Speed
- 120MHz core(ARM946ES) operation, 60MHz bus operation
- Supportable Engine Speed : under 30ppm
* Dual bus architecture for bus traffic distribution
- AMBA High performance Bus (AHB)
- System Bus with SDRAM
* Integrated ARM946ES
- 32-bit RISC embedded processor core
- 16KB instruction cache and 16KB data cache
- No Tightly Coupled Memory
- Memory Protection Unit & CP15 control program
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